Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

ABSTRACT

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/720,820, filed on May 24, 2015, which is a divisional of U.S. patentapplication Ser. No. 13/629,141, filed on Sep. 27, 2012, now U.S. Pat.No. 9,041,106, issued on May 26, 2015, the entire contents of which arehereby incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the invention are in the field of semiconductor devicesand, in particular, three-dimensional germanium-based semiconductordevices formed on globally or locally isolated substrates.

BACKGROUND

For the past several decades, the scaling of features in integratedcircuits has been a driving force behind an ever-growing semiconductorindustry. Scaling to smaller and smaller features enables increaseddensities of functional units on the limited real estate ofsemiconductor chips. For example, shrinking transistor size allows forthe incorporation of an increased number of memory devices on a chip,lending to the fabrication of products with increased capacity. Thedrive for ever-more capacity, however, is not without issue. Thenecessity to optimize the performance of each device becomesincreasingly significant.

In the manufacture of integrated circuit devices, multi-gatetransistors, such as tri-gate transistors, have become more prevalent asdevice dimensions continue to scale down. In conventional processes,tri-gate transistors are generally fabricated on either bulk siliconsubstrates or silicon-on-insulator substrates. In some instances, bulksilicon substrates are preferred due to their lower cost and becausethey enable a less complicated tri-gate fabrication process. In otherinstances, silicon-on-insulator substrates are preferred because of theimproved short-channel behavior of tri-gate transistors.

Silicon-on-insulator substrates, formed either by global isolation orlocal isolation, may also be used to fabricate gate-all-around devices.Many different techniques have been attempted to fabricate suchthree-dimensional isolated channel devices. However, significantimprovements are still needed in the area of isolation formation forsuch semiconductor devices.

In another aspect, many different techniques have been attempted toimprove the mobility of transistors. However, significant improvementsare still needed in the area of electron and/or hole mobilityimprovement for semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1K illustrate cross-sectional views of various operations in amethod of fabricating a semiconductor device, in accordance with anembodiment of the present invention.

FIGS. 2A-2K illustrate cross-sectional views of various operations inanother method of fabricating a semiconductor device, in accordance withan embodiment of the present invention.

FIGS. 3A-3G illustrate cross-sectional views of various operations inanother method of fabricating a semiconductor device, in accordance withan embodiment of the present invention.

FIG. 4A illustrates a three-dimensional cross-sectional view of ananowire-based semiconductor structure, in accordance with an embodimentof the present invention.

FIG. 4B illustrates a cross-sectional channel view of the nanowire-basedsemiconductor structure of FIG. 4A, as taken along the a-a′ axis, inaccordance with an embodiment of the present invention.

FIG. 4C illustrates a cross-sectional spacer view of the nanowire-basedsemiconductor structure of FIG. 4A, as taken along the b-b′ axis, inaccordance with an embodiment of the present invention.

FIG. 5 illustrates a computing device in accordance with oneimplementation of an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Three-dimensional germanium-based semiconductor devices formed onglobally or locally isolated substrates are described. In the followingdescription, numerous specific details are set forth, such as specificintegration and material regimes, in order to provide a thoroughunderstanding of embodiments of the present invention. It will beapparent to one skilled in the art that embodiments of the presentinvention may be practiced without these specific details. In otherinstances, well-known features, such as integrated circuit designlayouts, are not described in detail in order to not unnecessarilyobscure embodiments of the present invention. Furthermore, it is to beunderstood that the various embodiments shown in the Figures areillustrative representations and are not necessarily drawn to scale.

One or more embodiments of the present invention are directed to theintegration of silicon germanium (SiGe) or germanium (Ge)three-dimensional body structures (e.g., FINs) on isolated substrates.For example, such three-dimensional germanium-containing semiconductorbodies may be fabricated above, but isolated from, an underlying bulksubstrate by using a silicon-on-insulator (SOI) or anunder-fin-oxidation (UFO) approach. The germanium-containingsemiconductor bodies may be essentially entirely composed of germanium,or may be substantially composed of germanium. In an embodiment, agermanium-containing semiconductor body is composed of at least 50%germanium, such as in Si_(x)Ge_(y) (y>0.5), and possibly greater than70% germanium. In other embodiments, the germanium-containingsemiconductor body is composed of at least 98% germanium. In anembodiment, the germanium-containing semiconductor body is suitable oroptimal for hole carrier mobility, e.g., as in PMOS type semiconductordevices.

Process flows described herein may be applicable to tri-Gate and FIN-FETtransistors for, e.g., 14 nanometer node and smaller device generations.One or more embodiments involve deposition of a SiGe or Ge FIN (e.g., agermanium-containing FIN) on a silicon (Si) buffer or release layer andselectively removing the Si buffer or release layer in subsequentprocessing to enable fabrication of a SiGe or Ge FIN gate-all-around orcontact-all-around structure or device. An additional Si buffer may alsobe deposited on the top of the FIN as well if needed to act a protectivetop layer and, subsequently, may be selectively removed. Not allportions of the Si release or buffer layer are necessarily removed fromunderneath the germanium-containing semiconductor body, e.g., portionsmay remain under gate spacers.

In general, one or more embodiments are directed at fabricating SiGe orGe material channels in a FIN structure. It may be advantageous to havea SiGe or Ge FIN on an SiO₂ substrate in order for taking advantage offully undoped channels (e.g., with no subFIN leakage) and minimized gateinduced drain leakage (GIDL) or junction leakage. However, SiGe or Gemay not be grown epitaxially on SiO₂ (e.g., to form an SOI-likesubstrate). Furthermore, under fin oxidation approaches may have to beperformed with care taken to avoid having a formed oxide coming incontact with the SiGe or Ge. Such contact may otherwise induce SiGecondensation (e.g., Ge % non-uniformity), the generation of GeO₂ or GeO,both very poor oxides with respect to transistor performance.

Embodiments described herein can involve deposition of SiGe or Ge over aSi buffer layer (if from an SOI substrate) or over an Si wafer (if EPIsubstrate+UFO) and subsequent removal of the Si layer with a selectiveSi etch process. Such approaches enable the opportunity to fabricategate-all-around FIN structures in the gate and/or a contact-all-aroundstructure in the source and drain regions (S/D).

A variety of approaches may be used to fabricate three-dimensionalgermanium-based semiconductor devices formed on globally or locallyisolated substrates. For example, in FIGS. 3A-3G describe below, anintervening insulating layer has already been formed prior to formationof a germanium-containing semiconductor body layer. In otherembodiments, such as the case for the process schemes described inassociation with FIGS. 1A-1K and 2A-2K below, an intervening insulatinglayer is formed subsequent to germanium-containing semiconductor bodyformation. Thus, one or more embodiments of the present invention aredirected to a plurality of semiconductor devices havingthree-dimensional germanium-containing bodies or active regions (e.g.,FINs) formed above a bulk substrate, such as a bulk single crystallinesilicon substrate. One or more of the plurality of devices is subjectedto an under fin oxidation (UFO, described in greater detail below)process to isolate, or at least restrict, the device from the underlyingbulk substrate. Accordingly, one or more embodiments include fabricationprocesses using a selective (versus global) UFO process to provideselective substrate isolation for targeted devices. However, otherembodiments are directed to a plurality of semiconductor devices havingthree-dimensional germanium-containing bodies or active regions formedon a globally insulating substrate.

Furthermore, in some embodiments, such as the case for the processschemes described in association with FIGS. 1A-1K, 2A-2K and 3A-3Gbelow, a gate electrode is fabricated following release of a portion ofa germanium-containing semiconductor body layer, enabling formation of,e.g., gate-all-around semiconductor devices. Thus, focusing on agate-all-around aspect of embodiments and/or contact-all-around aspectof embodiments of the present invention, different approaches areavailable to provide a gate surrounding a channel region or a contactsurrounding a source/drain region, or both. Also, the gate-all-aroundand contact-all-around structure is expected to improve short channelperformance and transistor contact resistance (e.g., reduce Rexternal).As such, high performance, low leakage transistor technology approachesare described herein.

In a first example utilizing a UFO approach, FIGS. 1A-1K illustratecross-sectional views of various operations in a method of fabricating athree-dimensional germanium-containing semiconductor device, inaccordance with an embodiment of the present invention. Referring toFIG. 1A, a starting semiconductor structure 100 includesgermanium-containing semiconductor bodies 106, such as germanium (Ge) orsilicon germanium (SiGe) fins, disposed on a semiconductor substrate102, such as a bulk silicon substrate. A hardmask layer 110, such as asilicon nitride hardmask layer, is disposed on the germanium-containingsemiconductor bodies 106. Spacers 112, such as silicon nitride spacersare formed along the sidewalls of the germanium-containing semiconductorbodies 106, as depicted in FIG. 1B, e.g., by conformal layer depositionand etch back. Referring to FIG. 1C, exposed portions of the substrate102 are removed to provide semiconductor pedestals 120 underneath thesemiconductor bodies 106. For example, in the case that thegermanium-containing semiconductor bodies 106 are protected by siliconnitride hardmask and spacers, the silicon semiconductor pedestals 120may be formed selectively without impacting the germanium-containingsemiconductor bodies 106. The semiconductor pedestals 120 are thenoxidized to form isolation pedestals 122 with bird's beak portions 123,as depicted in FIG. 1D. Oxidation may also occur in the top portion ofthe remaining substrate 102, as is also depicted in FIG. 1D. However,oxidation at the upper portion of the semiconductor pedestals 120 isincomplete (e.g., resulting in bird's beak portions 123), leavingsilicon release layer 105. Referring to FIG. 1E, the spacers andhardmask are removed to leave isolation pedestals 122/123, siliconrelease layer 105, and germanium-containing semiconductor bodies 106remaining. Focusing the remainder of the description on only onegermanium-containing semiconductor body 106, a dielectric pattern 130may be formed to surround the semiconductor body 106, silicon releaselayer 105, and isolation pedestal 122/123, as depicted in FIG. 1F, e.g.,an inter-layer dielectric (ILD) pattern. The bird's beak portions 123 ofthe isolation pedestal 122 are then removed, as depicted in FIG. 1G,e.g., by using an HF solution to remove the oxide. It is to beunderstood that a portion of the remaining isolation pedestal 122 mayalso be eroded. Referring to FIG. 1H, portions of the silicon releaselayer 105 are selectively removed to provide an entirely exposed portion132 of the germanium-containing semiconductor body 106 above isolationpedestal 122. For example, in one embodiment, the portion of the siliconrelease layer 105 under the channel region of the germanium-containingsemiconductor body 106 is removed, e.g., to ultimately enable formationof a gate-all-around structure. In another embodiment, the portions ofthe silicon release layer 105 under the source/drain regions of thegermanium-containing semiconductor body 106 are removed, e.g., toultimately enable formation of a contact-all-around structure. Inanother embodiment, at different stages in a process flow, the portionof the silicon release layer 105 under the channel region of thegermanium-containing semiconductor body 106 is removed and the portionsof the silicon release layer 105 under the source/drain regions of thegermanium-containing semiconductor body 106 are removed, e.g., toultimately enable formation of a gate-all-around and acontact-all-around structure. Using the first case as an example, a gatestack 140 is formed within the structure of FIG. 1H to provide agate-all-around structure 140, as depicted in FIG. 1I. The gate stack140 includes a gate dielectric layer 142 and a gate electrode 144material surrounding the channel region 132 of the germanium-containingsemiconductor body 106. At a different stage in the process flow, asdepicted in FIG. 1J, the portions of the silicon release layer 105 underthe source and drain regions 160 are removed to enable ultimateformation of a contact-all-around structure. Referring to FIG. 1K, inthe case that the gate stack 140 is not permanent, the gate stack may bereplaced with a permanent gate stack 170, such as a high-k and metalgate stack.

It is to be understood that following FIG. 1E above, differentcombinations of the operations shown in FIGS. 1F-1J may be selected forprocessing. For example, the source and drain regions of thegermanium-containing semiconductor body 106 may be replaced withepitaxial regions. Also, the portions of the silicon release layer 105under regions 160 need not be removed. Additionally, referring to FIG.1J as an example, artifacts from processing may remain. As an example,regions 105A of the silicon release layer 105 may remain underneath gateelectrode spacers 165. Overall, in a general embodiment however, FIGS.1A-1K illustrate an exemplary process flow in which a sacrificialsilicon layer is used only at the bottom of a germanium-containing finstructure. FIGS. 1J and 1K represent a comparison between the FIN cut(1J) and poly cut (1K) cross-sectional views, with the former showingthe Si layer remaining under the spacer and the possibility to create atrench contact wrap around structure in the source and drain area toreduce external resistance.

Referring again to FIG. 1D, in an embodiment, the exposed portions ofthe semiconductor pedestals 120 are oxidized to form the isolationpedestals 122 by “under fin oxidation” (UFO). In an embodiment, the useof spacers may be required if a same or like material is being oxidized,and may even be included if non-like materials are used. In anembodiment, an oxidizing atmosphere or an adjacent oxidizing materialmay be used for UFO. However, in another embodiment, oxygen implant isused. In some embodiments, a portion of a material is recessed prior toUFO which may reduce the extent of so-called birds-beak formation duringoxidation. Thus, the oxidation may be performed directly, by recessingfirst, or by oxygen implant, or a combination thereof. In anotherembodiment, in place of UFO, selective removal of a material at thebottom of the fin (e.g., a material that has been previously depositedon the silicon wafer before an additional fin material deposition, suchas silicon germanium on a silicon substrate) is performed and replacedwith a dielectric material, such as silicon dioxide or silicon nitride.In either the UFO case or the selective material removal case, thelocation where reoxidation or material replacement is performed canvary. For example, in one such embodiment, the reoxidation or materialremoval is carried out post gate etch, post spacer etch, at an undercutlocation, at a replacement gate operation, or at a through contactoperation, or a combination thereof.

Referring again to FIG. 1H, in an embodiment, a portion of the siliconrelease layer 105 is etched selectively with a wet etch that selectivelyremoves the silicon release layer 105 portion while not etching thegermanium-containing body 106. Etch chemistries such as aqueoushydroxide chemistries, including ammonium hydroxide and potassiumhydroxide, for example, may be utilized to selectively etch the silicon.Thus, a silicon layer may be removed from a silicon germanium orgermanium fin-type structure.

Referring again to FIGS. 1F-1K, gate stack structures may be fabricatedby a replacement gate process. In such a scheme, dummy gate materialsuch as polysilicon or silicon nitride pillar material, may be removedand replaced with permanent gate electrode material. In one suchembodiment, a permanent gate dielectric layer is also formed in thisprocess, as opposed to being carried through from earlier processing. Inan embodiment, dummy gates are removed by a dry etch or wet etchprocess. In one embodiment, dummy gates are composed of polycrystallinesilicon or amorphous silicon and are removed with a dry etch processcomprising SF₆. In another embodiment, dummy gates are composed ofpolycrystalline silicon or amorphous silicon and are removed with a wetetch process comprising aqueous NH₄OH or tetramethylammonium hydroxide.In one embodiment, dummy gates are composed of silicon nitride and areremoved with a wet etch including aqueous phosphoric acid.

In a second example utilizing a UFO approach, FIGS. 2A-2K illustratecross-sectional views of various operations in a method of fabricating athree-dimensional germanium-containing semiconductor device, inaccordance with an embodiment of the present invention. Referring toFIG. 2A, a starting semiconductor structure 200 includesgermanium-containing semiconductor bodies 206, such as germanium (Ge) orsilicon germanium (SiGe) fins, disposed on a semiconductor substrate202, such as a bulk silicon substrate. A top semiconductor release layer205B, such as a top silicon release layer, is disposed on thegermanium-containing semiconductor bodies 206. A hardmask layer 210,such as a silicon nitride hardmask layer, is disposed on the topsemiconductor release layer 205B. Spacers 212, such as silicon nitridespacers are formed along the sidewalls of the germanium-containingsemiconductor bodies 206, as depicted in FIG. 2B, e.g., by conformallayer deposition and etch back. Referring to FIG. 2C, exposed portionsof the substrate 202 are removed to provide semiconductor pedestals 220underneath the semiconductor bodies 206. For example, in the case thatthe germanium-containing semiconductor bodies 206 are protected bysilicon nitride hardmask and spacers, the silicon semiconductorpedestals 220 may be formed selectively without impacting thegermanium-containing semiconductor bodies 206. The semiconductorpedestals 220 are then oxidized to form isolation pedestals 222 withbird's beak portions 223, as depicted in FIG. 2D. Oxidation may alsooccur in the top portion of the remaining substrate 202, as is alsodepicted in FIG. 2D. However, oxidation at the upper portion of thesemiconductor pedestals 220 is incomplete (e.g., resulting in bird'sbeak portions 223), leaving bottom silicon release layer 205A. Referringto FIG. 2E, the spacers and hardmask are removed to leave isolationpedestals 222/223, bottom silicon release layer 205A, top siliconrelease layer 205B, and germanium-containing semiconductor bodies 206remaining. Focusing the remainder of the description on only onegermanium-containing semiconductor body 206, a dielectric pattern 230may be formed to surround the semiconductor body 206, silicon releaselayers 205A and 205B, and isolation pedestal 222/223, as depicted inFIG. 2F, e.g., an inter-layer dielectric (ILD) pattern. The bird's beakportions 223 of the isolation pedestal 222 are then removed, as depictedin FIG. 2G, e.g., by using an HF solution to remove the oxide. It is tobe understood that a portion of the remaining isolation pedestal 222 mayalso be eroded. Referring to FIG. 2H, portions of the silicon releaselayers 205A and 205B are selectively removed to provide an entirelyexposed portion 232 of the germanium-containing semiconductor body 206above isolation pedestal 222. For example, in one embodiment, theportions of the silicon release layers 205A and 205B under and above thechannel region of the germanium-containing semiconductor body 206 areremoved, e.g., to ultimately enable formation of a gate-all-aroundstructure. In another embodiment, the portions of the silicon releaselayers 205A and 205B under and above the source/drain regions of thegermanium-containing semiconductor body 206 are removed, e.g., toultimately enable formation of a contact-all-around structure. Inanother embodiment, at different stages in a process flow, the portionsof the silicon release layers 205A and 205B under and above the channelregion of the germanium-containing semiconductor body 206 are removedand the portions of the silicon release layers 205A and 205B under andabove the source/drain regions of the germanium-containing semiconductorbody 206 are removed, e.g., to ultimately enable formation of agate-all-around and a contact-all-around structure. Using the first caseas an example, a gate stack 240 is formed within the structure of FIG.2H to provide a gate-all-around structure 240, as depicted in FIG. 2I.The gate stack 240 includes a gate dielectric layer 242 and a gateelectrode 244 material surrounding the channel region 232 of thegermanium-containing semiconductor body 206. At a different stage in theprocess flow, as depicted in FIG. 2J, the portions of the siliconrelease layers 205A and 205B under and above the source and drainregions 260 are removed to enable ultimate formation of acontact-all-around structure. Referring to FIG. 2K, in the case that thegate stack 240 is not permanent, the gate stack may be replaced with apermanent gate stack 270, such as a high-k and metal gate stack.

It is to be understood that following FIG. 2E above, differentcombinations of the operations shown in FIGS. 2F-2K may be selected forprocessing. For example, the source and drain regions of thegermanium-containing semiconductor body 206 may be replaced withepitaxial regions. Also, the portions of the silicon release layers 205Aand 205B under and above regions 260 need not be removed. Additionally,referring to FIG. 2J as an example, artifacts from processing mayremain. As an example, regions 205A′ and 205B′ of the silicon releaselayers 205A and 205B may remain underneath regions of gate electrodespacers 265. Overall, in a general embodiment however, FIGS. 2A-2Killustrate an exemplary process flow in which a sacrificial siliconlayer is used at both the top and the bottom of a germanium-containingfin structure. FIGS. 2J and 2K represent a comparison between the FINcut (2J) and poly cut (2K) cross-sectional views, with the formershowing the Si layer remaining under the spacer and the possibility tocreate a trench contact wrap around structure in the source and drainarea to reduce external resistance.

In an example utilizing already-formed buried oxide approach, FIGS.3A-3G illustrate cross-sectional views of various operations in anothermethod of fabricating a semiconductor device, in accordance with anembodiment of the present invention. Referring to FIG. 3A, a startingsemiconductor structure 300 includes germanium-containing semiconductorbodies 306, such as silicon germanium or germanium fins, disposed on asemiconductor release layer 305, such as a silicon release layer. Thesilicon release layer 305 is disposed on an insulating layer 304, suchas a buried SiO₂ layer of a silicon-on-insulator (SOI) substrate. Theinsulating layer 304 is disposed on a substrate 302, such as a siliconsubstrate. A hardmask layer 310, such as a silicon nitride hardmasklayer, is disposed on the germanium-containing semiconductor bodies 306.The silicon release layer 305 is patterned to expose insulating layer304, as depicted in FIG. 3B, e.g., by a dry etch process. Focusing theremainder of the description on only one germanium-containingsemiconductor body 306, the hardmask 310 is removed and a dielectricpattern 330 is formed to surround the germanium-containing semiconductorbody 306 and silicon release layer 305, as depicted in FIG. 3C, e.g., aninter-layer dielectric (ILD) pattern. Although not depicted in FIG. 3C,source and drain replacement and/or a replacement gate process may alsobe performed at, prior to or after, this stage. Referring to FIG. 3D,the silicon release layer 305 (and top silicon release layer if present,such as described in association with FIGS. 2A-2K) is removed. Then, agate dielectric layer 342 and metal gate electrode 344 may be formed, asdepicted in FIG. 3E. Referring to FIGS. 3F and 3G (latter is repeat ofFIG. 3E), respectively, a comparison between the FIN cut 380 and polycut 390 views is provided. In the former view, the possibility tofabricate a trench contact wrap-around is available in the source anddrain (S/D) regions. Other features may be as described above inassociation with FIGS. 1J/1K and 2J/2K.

It is to be understood that additional wire structures (such as thosedescribed below in association with FIGS. 4A-4C) may also be fabricatedin association with the fin structures described and illustrated inFIGS. 1A-1K, 2A-2K and 3A-3G above. As an example, FIG. 4A illustrates athree-dimensional cross-sectional view of a nanowire-based semiconductorstructure, in accordance with an embodiment of the present invention.FIG. 4B illustrates a cross-sectional channel view of the nanowire-basedsemiconductor structure of FIG. 4A, as taken along the a-a′ axis. FIG.4C illustrates a cross-sectional spacer view of the nanowire-basedsemiconductor structure of FIG. 4A, as taken along the b-b′ axis.

Referring to FIG. 4A, a semiconductor device 400 includes one or morevertically stacked nanowires (404 set) disposed above a substrate 402.Embodiments herein are targeted at both single wire devices and multiplewire devices. As an example, a three nanowire-based devices havingnanowires 404A, 404B and 404C is shown for illustrative purposes. Forconvenience of description, nanowire 404A is used as an example wheredescription is focused on only one of the nanowires. It is to beunderstood that where attributes of one nanowire are described,embodiments based on a plurality of nanowires may have the sameattributes for each of the nanowires.

Each of the nanowires 404 includes a germanium-containing channel region406 disposed in the nanowire. The germanium-containing channel region406 has a length (L). Referring to FIG. 4B, the germanium-containingchannel region also has a perimeter orthogonal to the length (L).Referring to both FIGS. 4A and 4B, a gate electrode stack 408 surroundsthe entire perimeter of each of the germanium-containing channel regions406 of nanowires 404C and 404B. In one embodiment, a semiconductorrelease layer 490 portion (described in greater detail above) is notpresent under the germanium-containing channel region 406 of nanowire404A, and the device 400 is thus a gate-all-around device with respectto the first nanowire 404A. In another embodiment, however, thesemiconductor release layer 490 portion is present under thegermanium-containing channel region 406 of nanowire 404A, and the device400 is thus not a gate-all-around device with respect to the firstnanowire 404A. The gate electrode stack 408 includes a gate electrodealong with a gate dielectric layer disposed between thegermanium-containing channel region 406 and the gate electrode (notshown).

Referring again to FIG. 4A, each of the nanowires 404 also includessource and drain regions 410 and 412, possibly germanium-containingsource and drain regions, disposed in the nanowire on either side of thegermanium-containing channel region 406. A pair of contacts 414 isdisposed over the source/drain regions 410/412. Referring to both FIGS.4A and 4B, the pair of contacts 414 is disposed over the source/drainregions 410/412. In one embodiment, a semiconductor release layer 490portion (described in greater detail above) is not present under thesource or drain region 410 or 412 of nanowire 404A, and the device 400is thus a contact-all-around device with respect to the first nanowire404A. In another embodiment, however, the semiconductor release layer490 portion is present under the source or drain region 410 or 412 ofnanowire 404A, and the device 400 is thus not a contact-all-arounddevice with respect to the first nanowire 404A.

Referring again to FIG. 4A, in an embodiment, the semiconductor device400 further includes a pair of spacers 416. The spacers 416 are disposedbetween the gate electrode stack 408 and the pair of contacts 414. Asdescribed above, the germanium-containing channel regions and thesource/drain regions are, in at least several embodiments, made to bediscrete. However, not all regions of the nanowires 404 need be, or evencan be made to be discrete. For example, referring to FIG. 4C, nanowires404A-404C are not discrete at the location under spacers 416. In oneembodiment, the stack of nanowires 404A-404C have interveningsemiconductor material 418 there between, such as silicon interveningbetween silicon germanium or germanium nanowires, or vice versa. In oneembodiment, the bottom nanowire 404A is still in contact with asemiconductor release layer 490 portion. Thus, in an embodiment, aportion of the plurality of vertically stacked nanowires under one orboth of the spacers is non-discrete.

The semiconductor release layer 490 may be a layer (or remnants thereof)such as the release layer 105/205/305 described above. In oneembodiment, the semiconductor release layer 490 is composed of siliconand the overlying nanowire 404A is composed of silicon germanium orgermanium. In an embodiment, portions of the semiconductor release layer490 are removed under the germanium-containing channel region ofnanowire 404A and a gate-all-around structure may be formed. In anembodiment, portions of the semiconductor release layer 490 are removedunder the source and drain regions of nanowire 404A and acontact-all-around structure may be formed. In an embodiment, portionsof the semiconductor release layer 490 are removed under the channel andthe source and drain regions of nanowire 404A and both a gate-all-aroundstructure and a contact-all-around structure may be formed.

In accordance with an embodiment of the present invention, the one ormore nanowires 404A-404C of the semiconductor device 400 are uniaxiallystrained nanowires. Thus, a semiconductor device may be fabricated froma single uniaxially strained nanowire (e.g., 404A) or from a pluralityof vertically stacked uniaxially strained nanowires (404A-404C), asdepicted in FIG. 4A. The uniaxially strained nanowire or plurality ofnanowires may be uniaxially strained with tensile strain or withcompressive strain. In an embodiment, a compressively uniaxiallystrained nanowire has a channel region composed of silicon germanium(Si_(x)Ge_(y), where 0<x<100, and 0<y<100) or germanium. In anembodiment, a PMOS semiconductor device is fabricated from a nanowirehaving the uniaxial compressive strain.

Referring to FIGS. 4A-4C, the semiconductor device 400 further includesa dielectric layer 430 disposed between a bulk substrate 402 and thenanowires 404A-404C. In an embodiment, the dielectric layer 430 iseffectively continuous across a substrate 402 and is a global insulatinglayer. In one embodiment, the dielectric layer 430 is composed of adielectric material such as, but not limited to, silicon dioxide,silicon oxy-nitride or silicon nitride. In another embodiment, thenanowires 404A-404C are isolated from a bulk substrate 402 by anisolation pedestal, e.g., they are locally isolated. The isolationpedestal may be composed of a material suitable to electrically isolateat least a portion, if not all, of the nanowire 404A from the bulksubstrate 402. For example, in one embodiment, the isolation pedestal iscomposed of a dielectric material such as, but not limited to, silicondioxide, silicon oxy-nitride or silicon nitride. In an embodiment, theisolation pedestal is composed of an oxide of the semiconductor materialof the bulk substrate 402.

In an embodiment, the term “isolation pedestal” is used to covey adiscrete isolation structure formed at a given time, e.g., a discretestructure formed only under a channel region, or a pair of discretestructures formed only under a pair of source and drain regions, or adiscrete structure formed under a channel region as well as under a pairof source and drain regions. In another embodiment, the term “isolationpedestal” is used to covey a combination of isolation structures formedat different times, e.g., a discrete structure formed under a channelregion in combination with a pair of discrete structures formed, at adifferent time, under a pair of source and drain regions.

Bulk substrate 402 may be composed of a semiconductor material that canwithstand a manufacturing process. In an embodiment, bulk substrate 402is composed of a crystalline silicon, silicon/germanium or germaniumlayer doped with a charge carrier, such as but not limited tophosphorus, arsenic, boron or a combination thereof. In one embodiment,the concentration of silicon atoms in bulk substrate 402 is greater than97%. In another embodiment, bulk substrate 402 is composed of anepitaxial layer grown atop a distinct crystalline substrate, e.g. asilicon epitaxial layer grown atop a boron-doped bulk siliconmono-crystalline substrate. Bulk substrate 402 may alternatively becomposed of a group III-V material. In an embodiment, bulk substrate 402is composed of a III-V material such as, but not limited to, galliumnitride, gallium phosphide, gallium arsenide, indium phosphide, indiumantimonide, indium gallium arsenide, aluminum gallium arsenide, indiumgallium phosphide, or a combination thereof. In one embodiment, bulksubstrate 402 is composed of a III-V material and the charge-carrierdopant impurity atoms are ones such as, but not limited to, carbon,silicon, germanium, oxygen, sulfur, selenium or tellurium. In anotherembodiment, bulk substrate 402 is undoped or only lightly doped.

In an embodiment, the gate electrode of gate electrode stack 408 iscomposed of a metal gate and the gate dielectric layer is composed of ahigh-K material. For example, in one embodiment, the gate dielectriclayer is composed of a material such as, but not limited to, hafniumoxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconiumoxide, zirconium silicate, tantalum oxide, barium strontium titanate,barium titanate, strontium titanate, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, lead zinc niobate, or a combination thereof.Furthermore, a portion of gate dielectric layer may include a layer ofnative oxide formed from the outer few layers of the semiconductornanowires 404A-404C. In an embodiment, the gate dielectric layer iscomposed of a top high-k portion and a lower portion composed of anoxide of a semiconductor material. In one embodiment, the gatedielectric layer is composed of a top portion of hafnium oxide and abottom portion of silicon dioxide or silicon oxy-nitride.

In one embodiment, the gate electrode is composed of a metal layer suchas, but not limited to, metal nitrides, metal carbides, metal silicides,metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum,ruthenium, palladium, platinum, cobalt, nickel or conductive metaloxides. In a specific embodiment, the gate electrode is composed of anon-workfunction-setting fill material formed above a metalworkfunction-setting layer.

The contacts 416 are, in an embodiment, fabricated from a metal species.The metal species may be a pure metal, such as nickel or cobalt, or maybe an alloy such as a metal-metal alloy or a metal-semiconductor alloy(e.g., such as a silicide material). In an embodiment, spacers 416 arecomposed of an insulative dielectric material such as, but not limitedto, silicon dioxide, silicon oxy-nitride or silicon nitride.

Semiconductor device 400 may be any semiconductor device incorporating agate, one or more channel regions and one or more pairs of source/drainregions. In an embodiment, semiconductor device 400 is one such as, butnot limited to, a MOS-FET, a memory transistor, or aMicroelectromechanical System (MEMS). In one embodiment, semiconductordevice 400 is a three-dimensional MOS-FET and is a stand-alone device oris one device in a plurality of nested devices. As will be appreciatedfor a typical integrated circuit, both N- and P-channel transistors maybe fabricated on a single substrate to form a CMOS integrated circuit.

Although the device 400 described above is for a single device, e.g., anNMOS or a PMOS device, a CMOS architecture may also be formed to includeboth NMOS and PMOS channel devices disposed on or above the samesubstrate. A plurality of such NMOS devices, however, may be fabricatedto have different semiconductor body heights and/or may be isolated fromor coupled to an underlying bulk substrate. Likewise, a plurality ofsuch PMOS devices may be fabricated to have different semiconductor bodyheights and/or may be isolated from or coupled to an underlying bulksubstrate. Furthermore, additional processing not shown may includeprocessing operations such as back-end interconnect formation andsemiconductor die packaging.

A CMOS architecture may also be formed to include both NMOS and PMOSnanowire-based devices disposed on or above the same substrate.Nanowire/nanoribbon structure may be formed by selective etching ofsacrificial layers from multilayer epitaxial stacks. The epitaxiallayers may be used as a channel or may be selectively removed to form agap for all-around gate structure. The isolation layer under epitaxialwires may provide electrical isolation and form a bottom gap forall-around gate. The simplest CMOS integration scheme employs N/P MOSchannels fabricated with the same material. The process is simpler tofabricate in that it employs a single selective etch. However, straintechnology may be required to boost device performance. In accordancewith an embodiment of the present invention, the unique features of astarting material stack are exploited to integrate different NMOS andPMOS channel materials which are optimized for higher mobility. Forexample, in one embodiment, a sacrificial layer of an NMOS device isused as a PMOS channel and a sacrificial layer of a PMOS device is usedas an NMOS channel. Since the sacrificial layer may be removed duringprocessing, independent choice of channel materials and optimization ismade possible.

In general, one or more embodiments described herein can be implementedimprove performance on, e.g., 14 nanometer and smaller node products andreduce standby leakage. Standby leakage reduction may be particularlyimportant for system-on-chip (SOC) products with extremely stringentstandby power requirements. Furthermore, other or the same embodimentsmay take advantage of higher mobility properties of channel materialengineering using SiGe or Ge a hole carrier channel material. Also, thegate-all-around and/or contact-all-around structures are expected toimprove short channel performance and transistor contact resistance.

One or more embodiments of the present invention are directed atimproving the channel mobility for PMOS transistors. Mobility may beimproved using a germanium-containing semiconductor material, e.g., inthe channel region. Thus, one or more approaches described hereinprovide the appropriate high mobility material in the channel regionsfor PMOS transistors. In an embodiment, germanium-containing PMOSgate-all-around devices are provided.

FIG. 5 illustrates a computing device 500 in accordance with oneimplementation of the invention. The computing device 500 houses a board502. The board 502 may include a number of components, including but notlimited to a processor 504 and at least one communication chip 506. Theprocessor 504 is physically and electrically coupled to the board 502.In some implementations the at least one communication chip 506 is alsophysically and electrically coupled to the board 502. In furtherimplementations, the communication chip 506 is part of the processor504.

Depending on its applications, computing device 500 may include othercomponents that may or may not be physically and electrically coupled tothe board 502. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

The communication chip 506 enables wireless communications for thetransfer of data to and from the computing device 500. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 506 may implement anyof a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 500 may include a plurality ofcommunication chips 506. For instance, a first communication chip 506may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 506 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 504 of the computing device 500 includes an integratedcircuit die packaged within the processor 504. In some implementationsof the invention, the integrated circuit die of the processor includesone or more devices, such as MOS-FET transistors built in accordancewith implementations of the invention. The term “processor” may refer toany device or portion of a device that processes electronic data fromregisters and/or memory to transform that electronic data into otherelectronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit diepackaged within the communication chip 506. In accordance with anotherimplementation of the invention, the integrated circuit die of thecommunication chip includes one or more devices, such as MOS-FETtransistors built in accordance with implementations of the invention.

In further implementations, another component housed within thecomputing device 500 may contain an integrated circuit die that includesone or more devices, such as MOS-FET transistors built in accordancewith implementations of the invention.

In various implementations, the computing device 500 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 500 may be any other electronic device that processes data.

Thus, embodiments of the present invention include three-dimensionalgermanium-based semiconductor devices formed on globally or locallyisolated substrates.

In an embodiment, a semiconductor device includes a semiconductorsubstrate. An insulating structure is disposed above the semiconductorsubstrate. A three-dimensional germanium-containing body is disposed ona semiconductor release layer disposed on the insulating structure. Thethree-dimensional germanium-containing body includes a channel regionand source/drain regions on either side of the channel region. Thesemiconductor release layer is under the source/drain regions but notunder the channel region. The semiconductor release layer is composed ofa semiconductor material different from the three-dimensionalgermanium-containing body. A gate electrode stack surrounds the channelregion with a portion disposed on the insulating structure and laterallyadjacent to the semiconductor release layer.

In one embodiment, the insulating structure includes a global insulatinglayer.

In one embodiment, the insulating structure includes one or moreisolation pedestals.

In one embodiment, the semiconductor release layer is composedessentially entirely of silicon, and the three-dimensionalgermanium-containing body is composed of greater than approximately 50%germanium.

In one embodiment, the three-dimensional germanium-containing body iscomposed of greater than approximately 70% germanium.

In one embodiment, the semiconductor structure further includes a pairof insulating spacers. One spacer is disposed between the gate electrodeand the source region. The other spacer is disposed between the gateelectrode and the drain region. The semiconductor release layer extendsunderneath each of the pair of spacers.

In one embodiment, the semiconductor structure further includes a pairof conducting contacts. One contact is disposed on and partiallysurrounds the source region. The other contact is disposed on andpartially surrounds the drain region.

In one embodiment, the semiconductor structure further includes one ormore nanowires disposed in a vertical arrangement above thethree-dimensional germanium-containing body. The gate electrode stacksurrounds a channel region of each of the one or more nanowires.

In one embodiment, the gate electrode stack includes a high-k gatedielectric layer and a metal gate electrode.

In an embodiment, a semiconductor device includes a semiconductorsubstrate. An insulating structure is disposed above the semiconductorsubstrate. A three-dimensional germanium-containing body is disposed ona semiconductor release layer disposed on the insulating structure. Thethree-dimensional germanium-containing body includes a channel regionand source/drain regions on either side of the channel region. Thesemiconductor release layer is under the channel region but not underthe source/drain regions. The semiconductor release layer is composed ofa semiconductor material different from the three-dimensionalgermanium-containing body. A gate electrode stack partially surroundsthe channel region. A pair of conducting contacts is included. Onecontact is disposed on and surrounds the source region. The othercontact is disposed on and surrounds the drain region. A portion of eachof the pair of contacts is disposed on the insulating structure andlaterally adjacent to the semiconductor release layer.

In one embodiment, the insulating structure includes a global insulatinglayer.

In one embodiment, the insulating structure includes one or moreisolation pedestals.

In one embodiment, the semiconductor release layer is composedessentially of silicon. The three-dimensional germanium-containing bodyis composed of greater than approximately 50% germanium.

In one embodiment, the three-dimensional germanium-containing body iscomposed of greater than approximately 70% germanium.

In one embodiment, the semiconductor structure further includes a pairof insulating spacers. One spacer is disposed between the gate electrodeand the source region. The other spacer is disposed between the gateelectrode and the drain region. The semiconductor release layer extendsunderneath each of the pair of spacers.

In one embodiment, the semiconductor structure further includes one ormore nanowires disposed in a vertical arrangement above thethree-dimensional germanium-containing body. The gate electrode stacksurrounds a channel region of each of the one or more nanowires.

In one embodiment, the gate electrode stack includes a high-k gatedielectric layer and a metal gate electrode.

In an embodiment, a semiconductor device includes a semiconductorsubstrate. An insulating structure is disposed above the semiconductorsubstrate. A three-dimensional germanium-containing body is disposed ona semiconductor release layer disposed on the insulating structure. Thethree-dimensional germanium-containing body includes a channel regionand source/drain regions on either side of the channel region. Thesemiconductor release layer is not under the channel region and notunder the source/drain regions. The semiconductor release layer iscomposed of a semiconductor material different from thethree-dimensional germanium-containing body. A gate electrode stacksurrounds the channel region with a portion disposed on the insulatingstructure. A pair of conducting contacts is included. One contact isdisposed on and surrounds the source region. The other contact isdisposed on and surrounds the drain region. A portion of each of thepair of contacts is disposed on the insulating structure. A pair ofinsulating spacers is included. One spacer is disposed between the gateelectrode and the source region. The other spacer is disposed betweenthe gate electrode and the drain region. The semiconductor release layeris disposed underneath each of the pair of spacers and laterallyadjacent to a portion of the gate electrode stack and a portion of eachof the conducting contacts.

In one embodiment, the insulating structure includes a global insulatinglayer.

In one embodiment, the insulating structure includes one or moreisolation pedestals.

In one embodiment, the semiconductor release layer is composedessentially of silicon. The three-dimensional germanium-containing bodyis composed of greater than approximately 50% germanium.

In one embodiment, the three-dimensional germanium-containing body iscomposed of greater than approximately 70% germanium.

In one embodiment, the semiconductor structure further includes one ormore nanowires disposed in a vertical arrangement above thethree-dimensional germanium-containing body. The gate electrode stacksurrounds a channel region of each of the one or more nanowires.

In one embodiment, the gate electrode stack includes a high-k gatedielectric layer and a metal gate electrode.

In an embodiment, a method of fabricating a semiconductor deviceincludes forming a three-dimensional germanium-containing semiconductorstructure on semiconductor release layer disposed above a semiconductorsubstrate. The semiconductor release layer is composed of asemiconductor material different from the three-dimensionalgermanium-containing semiconductor structure. The method also includesinsulating the three-dimensional germanium-containing semiconductorstructure from the semiconductor substrate. The method also includes,subsequently, removing a portion of the semiconductor release layer. Themethod also includes forming a gate electrode stack at least partiallysurrounding a channel region of the three-dimensionalgermanium-containing semiconductor structure. The method also includesforming a pair of conducting contacts, one contact at least partiallysurrounding a source region of the three-dimensionalgermanium-containing semiconductor structure, and the other contact atleast partially surrounding a drain region of the three-dimensionalgermanium-containing semiconductor structure.

In one embodiment, insulating the three-dimensional germanium-containingsemiconductor structure includes providing a global insulating layer onthe semiconductor substrate.

In one embodiment, insulating the three-dimensional germanium-containingsemiconductor structure includes forming one or more isolationpedestals.

In one embodiment, forming the gate electrode stack includes using areplacement gate process. In one embodiment, removing the portion of thesemiconductor release layer includes removing a portion between thechannel region and the semiconductor substrate, and the gate electrodestack surrounds the channel region.

In one embodiment, removing the portion of the semiconductor releaselayer includes removing a portion between the source and drain regionsand the semiconductor substrate, and the one contact surrounds thesource region and the other contact surrounds the drain region.

What is claimed is:
 1. A semiconductor structure, comprising: asemiconductor substrate; an insulating structure disposed above thesemiconductor substrate; a semiconductor layer disposed over anddirectly on the insulating structure; a semiconductor body disposed onthe semiconductor layer, the semiconductor body comprising a channelregion and source/drain regions on both sides of the channel region,wherein the semiconductor layer is under the source/drain regions butnot under the channel region, the semiconductor layer comprising asemiconductor material different from the semiconductor body; and a gateelectrode stack surrounding the channel region with a portion disposedon the insulating structure directly below the channel region, andlaterally adjacent to the semiconductor layer.
 2. The semiconductorstructure of claim 1, wherein the insulating structure comprises aglobal insulating layer.
 3. The semiconductor structure of claim 1,wherein the insulating structure comprises one or more isolationpedestals.
 4. The semiconductor structure of claim 1, wherein thesemiconductor body comprises greater than approximately 70% germanium.5. The semiconductor structure of claim 1, further comprising: a pair ofinsulating spacers, one spacer disposed between the gate electrode andthe source region, and the other spacer disposed between the gateelectrode and the drain region, wherein the semiconductor layer extendsunderneath each of the pair of spacers.
 6. The semiconductor structureof claim 1, further comprising: a pair of conducting contacts, onecontact disposed on and partially surrounding the source region, and theother contact disposed on and partially surrounding the drain region. 7.The semiconductor structure of claim 1, further comprising: one or morenanowires disposed in a vertical arrangement above the semiconductorbody, wherein the gate electrode stack surrounds a channel region ofeach of the one or more nanowires.
 8. The semiconductor structure ofclaim 1, wherein the gate electrode stack comprises a high-k gatedielectric layer and a metal gate electrode.
 9. A semiconductorstructure, comprising: a semiconductor substrate; an insulatingstructure disposed above the semiconductor substrate; a semiconductorlayer disposed over and directly on the insulating structure; asemiconductor body disposed on the semiconductor layer, thesemiconductor body comprising a channel region and source/drain regionson both sides of the channel region, wherein the semiconductor layer isunder the channel region but not under the source/drain regions, thesemiconductor layer comprising a semiconductor material different fromthe semiconductor body; a gate electrode stack partially surrounding thechannel region; and a pair of conducting contacts, one contact disposedon and surrounding the source region, and the other contact disposed onand surrounding the drain region, wherein a portion of each of the pairof contacts is disposed on the insulating structure directly below thechannel region, and laterally adjacent to the semiconductor layer. 10.The semiconductor structure of claim 9, wherein the insulating structurecomprises a global insulating layer.
 11. The semiconductor structure ofclaim 9, wherein the insulating structure comprises one or moreisolation pedestals.
 12. The semiconductor structure of claim 9, whereinthe semiconductor body comprises greater than approximately 70%germanium.
 13. The semiconductor structure of claim 9, furthercomprising: a pair of insulating spacers, one spacer disposed betweenthe gate electrode and the source region, and the other spacer disposedbetween the gate electrode and the drain region, wherein thesemiconductor layer extends underneath each of the pair of spacers. 14.The semiconductor structure of claim 9, further comprising: one or morenanowires disposed in a vertical arrangement above the semiconductorbody, wherein the gate electrode stack surrounds a channel region ofeach of the one or more nanowires.
 15. The semiconductor structure ofclaim 9, wherein the gate electrode stack comprises a high-k gatedielectric layer and a metal gate electrode.
 16. A semiconductorstructure, comprising: a semiconductor substrate; an insulatingstructure disposed above the semiconductor substrate; a semiconductorlayer disposed over and directly on the insulating structure; asemiconductor body disposed on the semiconductor layer, thesemiconductor body comprising a channel region and source/drain regionson either side of the channel region, wherein the semiconductor layer isnot under the channel region and not under the source/drain regions, thesemiconductor layer comprising a semiconductor material different fromthe semiconductor body; a gate electrode stack surrounding the channelregion with a portion disposed on the insulating structure directlybelow the channel region; a pair of conducting contacts, one contactdisposed on and surrounding the source region, and the other contactdisposed on and surrounding the drain region, wherein a portion of eachof the pair of contacts is disposed on the insulating structure; and apair of insulating spacers, one spacer disposed between the gateelectrode and the source region, and the other spacer disposed betweenthe gate electrode and the drain region, wherein the semiconductor layeris disposed underneath each of the pair of spacers and laterallyadjacent to a portion of the gate electrode stack and a portion of eachof the conducting contacts.
 17. The semiconductor structure of claim 16,wherein the insulating structure comprises a global insulating layer.18. The semiconductor structure of claim 16, wherein the insulatingstructure comprises one or more isolation pedestals.
 19. Thesemiconductor structure of claim 16, further comprising: one or morenanowires disposed in a vertical arrangement above the semiconductorbody, wherein the gate electrode stack surrounds a channel region ofeach of the one or more nanowires.
 20. The semiconductor structure ofclaim 16, wherein the gate electrode stack comprises a high-k gatedielectric layer and a metal gate electrode.